A System Level Tool for Translating Software to Reconfigurable Hardware, Phase I

In this research we will develop a system level tool to translate binary code of a general-purpose processor into Register Transfer Level VHDL code to be mapped onto FPGA-based reconfigurable hardware. We further plan to study techniques for performing hardware/software co-design on integrated systems-on-a-chip platforms consisting of embedded processors, memories and FPGAs. Finally we will develop techniques to perform area, delay and power tradeoffs in the hardware that is synthesized by our compiler on the FPGAs. We will demonstrate our concepts using a prototype compiler that will translate binary code of a Texas Instrument TMS320 C6000 processor into a hardware/software implementation on a Xilinx Virtex II Pro Platform FPGA. This work will be performed jointly between BINACHIP, a small business company, and University of Illinois at Chicago, a partner research institution

This is a mature technology (TRL 7+) — the realistic path in is usually NASA's Technology Transfer Program: licensing an existing NASA patent, or a Space Act Agreement to use NASA facilities/expertise directly. NASA also runs a startup licensing program with no upfront fee for companies formed to commercialize a specific NASA technology.

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