Onboard Hardware Acceleration of Terrain Relative Navigation and Optical Navigation Algorithms with High-Level Synthesis for FPGAs

To enable planetary and exploration missions, high-rate onboard computation is required to provide more robust capability to support autonomous Guidance, Navigation, and Control (GN&C). This proposal will support FPGA-based hardware acceleration of both Terrain Relative Navigation (TRN) and Optical Navigation (OpNav) algorithms onto representative flight-like FPGA systems, using state-of-the-art FPGA productivity tools such as High-Level Synthesis (HLS) (i.e. C-to-RTL). This approach allows the team to use high-level C-based code, as opposed to low-level FPGA code, to perform broad design-space exploration of configurable algorithm parameters while rapidly prototyping unique FPGA designs, which produces more resource efficient execution for future mission and instrument systems.

Hardware acceleration of TRN/OpNav applications allows a system to process more images onboard, which could result in increased autonomy and a future possibility of more challenging mission concepts, even for smaller class satellites. Faster processing of incoming data could reduce operations costs by reducing number of operators needed during proximity operations. These rapid calculations can dramatically assist comparing captured images with pre-defined maps and navigating with respect to these landmarks, which will be essential for missions investigating smaller body targets. Finally, these improvements are essential for future mission concepts that require more dedicated processing for data-driven artificial-intelligence or machine-learning components integrated into the system.

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