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Completed TRL 3 (started at 3, targeting 3)
This project aims to aggressively reduce the size of the Power System Electronics (PSE), low-voltage telemetry, and housekeeping (HK) electronics. The goal is to combine multiple discrete analog, digital, and mixed-signal devices into a single smart, radiation hardened, system-on-a-chip (SOC) chip solution. Ultimately this effort seeks to produce a flight worthy rad-hard device that will replace several discrete components in current and future PSE designs thus reducing the size, mass, power, complexity, and cost. At a higher level the device will serve as a modular low-power data acquisition SOC, suitable for miniaturized instruments and spacecraft smart/automated housekeeping data collection.
The main benefits are the reduction of size, mass, and power over current state-of-the-art and the next generation of PSE cards. The proposed device will not only support current and future GSFC PSE architectures, but it will also benefits CubeSat instruments, CubeSat PSE designs, and PSE designs for lunar surface, planetary, and heliophysics payloads.
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This is early/mid-stage (TRL 3) — the most realistic path in is NASA SBIR/STTR, which funds small businesses and research institutions to develop technology aligned with NASA's needs (equity-free, phased funding). Check whether a current SBIR/STTR solicitation topic overlaps with this project's technology area, or contact the project directly (above) to ask.
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