3D Integrated Memristor Chip for Neuromorphic Processing

Technical Abstract: This SBIR project proposes an integrated, multi-functional and reprogrammable memristor array having a multilayered crossbar architecture to emulate biological synapses in a small scale. Passive memristor crossbar array will be integrated with necessary peripheral circuitry for control of resistance states of memristors for imitating synaptic weights of neural networks. The input-output signals will be modulated using appropriate field programmable gate array (FPGA) control. Our proposed work demonstrates a less costly FPGA controlled integrated neuromorphic processor chip design scheme using oxide based memristors and peripheral circuitry from traditional CMOS technology. The proposed 3D memristor architecture could provide a unique cross-bar array technology with reconfigurable memristors, with the resistance states of memristors controlled using an FPGA. The FPGA based system would allow for precise programming of the memristors for the training, and the available computing and memory resources for inferencing. The innovation is in the design and fabrication of oxide thin film based memristors for each layer, with some of the memristors exhibiting large off/on resistance ratios, some used for switching, and some with low off/on resistance ratio with large number of intermediate resistance states (depicting the synaptic weights). Innovative fabrication and packaging solutions will be considered in Phase 2 for developing a microsystem with unique low power neuromorphic computing capability with SWaP considerations for small satellites.

Neuromorphic computing is expected to enable NASA’s growing demands for artificial intelligence (AI) and machine learning (ML) on board space platforms to optimize and automate operations. A hardware based neuromorphic computing utilizing memristors provides a potential low power computing with integrated memory and decentralized operations. Such an architecture could be used for onboard learning to optimize communication and data processing capabilities in a cognitive system meeting the SWaP constraints in space systems.

The commercial product from this research is an ultra-power efficient and high-throughput hardware processor system for deep learning in a distributed computing setting. The proposed system will be appliable in areas, including UAVs for the US Air Force, systems for the Army and Navy, and many commercial systems such as communications systems, collaborative robotics, autonomous systems, and IoT.

This is early/mid-stage (TRL 4) — the most realistic path in is NASA SBIR/STTR, which funds small businesses and research institutions to develop technology aligned with NASA's needs (equity-free, phased funding). Check whether a current SBIR/STTR solicitation topic overlaps with this project's technology area, or contact the project directly (above) to ask.

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