A Charge Ramping Quantizer

Pacific Microchip Corp. proposes to develop an ADC implementing fundamentally new architecture employing a single stage voltage-to-charge-to-digital converter based on a charge ramping quantizer (CRQ). The CRQ removes traditional barriers such as large number of comparators (Flash architecture), slow binary search (SAR architecture), power hungry and slow continuous-time comparators and large silicon area consuming time-to-digital converters (temporal ADC). By removing these barriers and taking full benefit of modern CMOS processes, the CRQ offers a high sampling rate at greatly reduced power consumption. A single sub-ADC based on this architecture demonstrates over 4 times speed improvement compared to a SAR ADC. The project will target 8-bit resolution and 56GS/s rate. Instead of overdesigning, when seeking to maximize the performance, the ADC will rely on parameter calibration using a built-in CPU. On-chip phase locked loops (PLLs) will be used for clock synthesis. For convenient interfacing with field programmable gate arrays (FPGAs) at up to 64x8.8Gb/s, the ADC will include a JESD204B standard compliant interface. Phase I work will provide the proof of ADC feasibility – critical blocks will be implemented and verified at the targeted technology node. At Phase II, a silicon proven prototype ADC will be provided.

Space-based wireless satellite-to-satellite communication systems Space-to-Earth communication systems Earth observation instrumentation

Future communication systems Multiple input multiple output (MIMO) systems Synthetic aperture radars (SARs) in active sensors Passive microwave sensors Receivers for SDRs and 5G communication systems Fiber optic communication systems for 100-400Gb/s Surveillance instruments Communication and navigation satellites Test instruments such as digital sampling scopes

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