RadRISC: A Secure, Resilient RISC-V Processor Infrastructure for Space Operations

To address the needs of image processing and other data parallel scientific applications TCL proposes RadRISC a scalable architecture composed of simple cores based on the RISC-V ISA with a Single Instruction Multiple Data (SIMD) architecture similar in organization to modern GPU processors. The preliminary overall system architecture includes an array of RISC-V cores connected via a RapidIO fault tolerant switch which also enables connections to a fault tolerant external memory for program data and an independent fault tolerant memory for checkpointing. The RapidIO switch in RadRISC also provides a connection to the hardware root of trust and any connected I/O devices or peripherals. An emphasis will be placed on keeping the cores relatively simple as this will enable more effective fault tolerance. The introduction of architectural complexity is an invitation to increase the potential failure points in a given processor design. While RadRISC will have many robust reliability features it will not sacrifice performance. The targeted signal and image processing workloads will be highly data-parallel which drives a simple, in-order pipeline architecture for RadRISC in lieu of a complex out-of-order design to enable maximum performance-per-watt. Per-cycle performance will be further enhanced through the addition of a SIMD unit to take advantage of the data parallelism. Previous resilient processor architectures have focused on strictly protecting user code. However, the RadRISC hardware and software stack will protect code executed in machine mode, supervisor mode and user mode. This is enabled by the combination of the aforementioned hardware techniques as well as a series of compiler-driven software techniques. This compiler-centric approach allows us to subsequently compile all the software components required to operate the system. This system and software architecture can be modeled using Sandia National Laboratories’ Structural Simulation Toolkit (SST).

In addition to the prescribed in flight system architectures, the proposed approach is applicable to a number of other NASA-associated markets. Our proposed approach can also be applied to other mission critical systems. This includes robotic control systems for flight operations and landing vehicle operations. Further, with a sufficient degree of compute density, these devices can be extended to create autonomous robotic vehicles and to traditional autonomous satellite or deep space probe devices.

There are several non-NASA market that include the ability to adapt the IP to commercial space applications, the application of the technology to miniature satellites, the application of the technology to traditional aeronautics and the application of the technology to autonomous vehicle platforms. We may also apply this for national security environments associated with DoE NNSA applications.

This is early/mid-stage (TRL 3) — the most realistic path in is NASA SBIR/STTR, which funds small businesses and research institutions to develop technology aligned with NASA's needs (equity-free, phased funding). Check whether a current SBIR/STTR solicitation topic overlaps with this project's technology area, or contact the project directly (above) to ask.

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