Non-Volatile, Low Power, and High Density SiC Memory For Future Venus Missions

The Hot Operating Temperature Technology 2021 Program goal "is to develop and mature technologies that will enable, significantly enhance, or reduce technical risk for in-situ missions to high-temperature environments with temperatures of 500 degrees Celsius or higher for a period of at least 60 days" including "Low-Power Electrical Circuits (<1000 mW)". One major technology gap for long term Venus surface exploration is low-power high density digital memory. This proposal directly addresses this notable technical challenge. During HOTTech 1 NASA GRC successfully developed and prototyped the world's first and only digital memory circuits to demonstrate more than a few hours of operation at/above Venus surface temperature (460 °C) via its still-improving SiC JFET-R integrated circuit (IC) technology. While over a year of 500 °C Random Access Memory (RAM) operation was achieved, these first-prototype chips were too small in storage capacity (16 bits each chip) and too high in power consumption (~ 200 mW each chip) to practically benefit Venus surface mission concepts. Furthermore, these prototype chips are incapable of preserving stored data during short-duration loss of power. While not a show-stopper for the simplest future Venus lander missions, the inability of future Venus landers to locally store useful quantities science data and mission operations instructions locally is clearly a severe restriction/handicap compared with Mars lander operations that abundantly rely on local storage of such data prior to advantageously-timed orbiter/Earth transmission. LLISSE and SAEVE Venus lander mission concepts rely on immediate transmission of collected observations, without any ability to buffer/store data on the lander due to the impractically higher power required to store sufficient data quantities to improve/impact desired mission functionality. Most modern silicon memory chips can quickly read and write gigabytes of data, yet faithfully retain all data for years in the complete absence of electrical power (e.g., solid state disk drives). Room-T silicon memory chips that exhibit zero-power memory storage are broadly classified as Non-Volatile Random Access Memories (NVRAM). This proposed work will seek to develop and demonstrate the first 500 °C durable NVRAM technology and chips as enabling to future extreme environment missions. This SiC JFET-R NVRAM is planned to be capable of storing mission-relevant data for hours at Venus surface temperature (460 °C) even in the complete absence of any power supplied to the chip. Similar to their low-T silicon memory counterparts, the SiC NVRAM would only require power for active reading and writing operations, and perhaps (worst case) "stored content refresh" operations taking only a second or two of power for every hour or two sitting on the surface of Venus. Averaged over time, the NVRAM approach will permit more than 1000-fold reduction power for each bit over the present state-of-art 500 °C durable RAM approach. Furthermore, we will migrate the SiC JFET-R process towards stepper-based lithography that will enable additional 4-fold size reduction in chip area of each bit/cell. The Resistive Switching Device (RSD) approach has proven practical for silicon memories, including high temperature NVRAMs operated up to 300 °C (temperature-limited by the silicon semiconductor). In the first half of the project, we will systematically investigate RSD's made from Venus-durable materials and processing towards directly leveraging them into the proven 500 °C/Venus-durable NASA Glenn SiC JFET-R process flow. During the second half of the project, we will seek to implement a complete 500 °C durable SiC NVRAM chip with 1 kilobit storage capacity with total average power below 20 mW.

Developing Instrument or spacecraft technology to improve measurements for future planetary science missions

This is early/mid-stage (TRL 2) — the most realistic path in is NASA SBIR/STTR, which funds small businesses and research institutions to develop technology aligned with NASA's needs (equity-free, phased funding). Check whether a current SBIR/STTR solicitation topic overlaps with this project's technology area, or contact the project directly (above) to ask.

None of these are guaranteed paths for this specific project — TechPort itself doesn't have an "apply" button. Reaching out to the contact(s) above with a specific question is usually the fastest way to find out what's actually open.