X-Ray Speed-Reading: Integrated Readout Technology for Fast, Very Low-Noise, Megapixel X-Ray Imaging Detectors

The most recent biennial Physics of the Cosmos Program Annual Technology Report identifies “fast, low-noise, megapixel X-ray imaging arrays” as a top-priority technology development need for future PCOS strategic astrophysics missions. The Astro2020 Decadal Survey further recommended “an X-ray mission designed to complement the European Space Agency (ESA) Athena mission” as the joint top priority for a new line of Probe Class missions. Here, sensitive, high spatial resolution (<1” half power diameter; HPD) X-ray imaging across a wide field of view likely represents the most natural complement to Athena, although high spectral resolution (R~7500) measurements utilizing dispersive grating spectroscopy offer another route. In either case, translated to the detector focal plane array, these features require thick (>100um), fully depleted, small pixel size X-ray detectors with a combination of fast readout rate, low noise, high spatial resolution and large pixel number, which cannot be furnished by currently mature technologies. Despite recent progress in X-ray detector technology, significant improvements are still needed. In particular, state-of-the-art X-ray CCDs cannot deliver the frame rates required for future strategic missions such as the Advanced X-ray Imaging Satellite (AXIS), a probe-class mission concept conforming to the recommendations of Astro2020. At Stanford, we have recently developed advanced integrated readout electronics - the MIT CCD readout chip (MCRC) - which, by virtue of fast amplifiers and minimal parasitics, can increase the per-output pixel readout rate of X-ray CCDs to 5M pix/sec, while maintaining the required excellent low noise performance. The MCRC design complements the CCD technology being developed by the MIT Kavli X-ray group and MIT Lincoln Laboratories, which is a clear candidate for the focal plane instrumentation of AXIS and other potential probe class X-ray missions. The first prototype of the MCRC readout electronics has been submitted for manufacture and will be tested over the coming year. Further improvements are necessary, however, to advance the TRL of the combined detector-plus-readout system to the point that it is suitable for a full flight instrument. In our previous efforts, we have also studied a novel CCD output stage concept dubbed the Single electron Sensitive ReadOut (SiSeRO). We have recently demonstrated the first proof-of-principle operation of such a device, as well as the potential for sub-electron noise performance, and have integrated a SiSeRO-suitable drain readout input into the first prototype MCRC readout chip. Further development is now needed to support the development of detectors incorporating multiple SiSeRo devices and establish more firmly the potential of this new detector device class. Specifically, in this proposal we aim to make the following improvements to the MCRC readout platform: 1) hybrid integration with external, multichannel, highly integrated, high performance ADCs; 2) integration of a CMOS high voltage (~12 V) clock driver for the output stage reset pulse, to minimize the time required for reset; 3) integration of detector bias generators into the ASIC; 4) improved housekeeping and monitoring functions through the addition of a simple ADC; 5) capturing temperature and detector bias conditions at the front end; 6) performance improvements to the MCRC drain readout scheme, including the extension of that capability to JFET-based CCDs. The development is structured into two ASIC manufacturing submissions, where the first one will include test structures for features and performance improvements that will be integrated into the existing MCRC V1.0 padframe, so every one of its 8 channels would test a different component, for efficient testing in the existing test systems. The second submission would use the best candidates from the previous submission and produce a new MCRC V2.0 chip with enhanced capabilities.

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