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Ultra-Low Power Extreme Environment Capable Avionics System-on-a-Chip Project
Completed
TRL 3 (started at 2, targeting 3)
Description
Develop ultra-low-power, wide-temperature (-150° C to +250 ° C), digital System-on-a-Chip (SOC) ASIC technology in a high resolution, inherently rad-hard IBM Silicon-on-Insulator (SOI) CMOS process to enable next-generation flight electronics. Demonstrate main flight-system electronics (flight processor, high- and low-speed instrument interfaces) in a chip containing a Cortex-M0 microprocessor that has been synthesized using a custom wide-temperature digital logic library developed in the same high resolution IBM SOI CMOS process.
Benefits
The new SoC ASIC has a very good chance of setting NASA on a path to produce low-cost, ARM-based, SoC ASICs for avionics applications.
Details
| Program | Center Innovation Fund: JPL CIF (JPL CIF) |
| Lead organization | Jet Propulsion Laboratory, Pasadena, CA |
| Start date | 2012-10-01 |
| End date | 2013-10-01 |
Project contacts
Listed on TechPort itself — the most direct way to ask about this specific project.
How to get involved
This is early/mid-stage (TRL 3) — the most realistic path in is NASA SBIR/STTR, which funds small businesses and research institutions to develop technology aligned with NASA's needs (equity-free, phased funding). Check whether a current SBIR/STTR solicitation topic overlaps with this project's technology area, or contact the project directly (above) to ask.
None of these are guaranteed paths for this specific project — TechPort itself doesn't have an "apply" button. Reaching out to the contact(s) above with a specific question is usually the fastest way to find out what's actually open.