High Performance Spaceflight Computing - Implementation (HPSC-I)

Space-based computing has not kept pace with the needs of current and future NASA missions. The objective of the High-Performance Spaceflight Computing (HPSC) project is to develop a next-generation flight computing system that addresses computational performance, energy management, and fault tolerance requirements for NASA missions through 2040 and beyond. HPSC introduces a new flight computing architecture capable of delivering up to 100 times the computational capacity of current flight processors for the same power consumption, while providing extensibility and interoperability to support a wide range of mission needs. It serves as a cross-cutting advancement and technology multiplier, both amplifying the capabilities of existing spacecraft and enabling new mission profiles. Microchip’s HPSC System-on-Chip (SoC) will integrate compute subsystems, memory controllers, and peripheral interfaces within a compute cluster based on Microchip’s second-generation SoC design. The architecture includes multiple 64-bit RISC-V CPU cores for general application processing, a highly redundant system controller, and optional dedicated cores for real-time applications. The compute complex is optimized for fault-tolerant processing and includes integrated hardware security features such as an encryption engine for cryptographic applications and a root of trust for secure operations, including secure boot. All subsystems are interconnected through an on-chip fabric, and multiple devices can be linked to provide scalable compute performance and enhanced fault tolerance. The chip supports a wide range of low-speed and high-speed interfaces for connectivity to external peripherals and is fabricated using GlobalFoundries’ 12 nm LP+ process node to ensure onshore manufacturing security and radiation tolerance suitable for spaceflight missions. The HPSC platform will also provide a complete software stack, including the development toolchain, system controller software, an optimized Linux operating system, and a system-validated board support package (BSP). An evaluation platform will be made available to NASA to support software development, testing, and future Single Board Computer (SBC) development. Furthermore, the architecture will enable software reuse and portability between the HPSC and Microchip FPGA product lines.

HPSC is a NASA-led new flight computing architecture, which radically advances the capabilities of space-based computing. Enables significant capability advances in mission and science autonomy, intelligent vehicles, flagship science at discovery prices, crew assist, and much more. HPSC is a fault-tolerant 10-core RISC-V System-on-Chip (SoC) that offers extremely high performance per watt. HPSC will have a full defense grade security solution on chip100X the computational capacity of current flight processors for the same amount of power Unprecedented flexibility to trade among computational performance, energy management and fault tolerance Highly extensible; chiplets can be cascaded together and/or configured with specialized co-processors HPSC will be fabricated on a DMEA “trusted" foundry – GlobalFoundries Fab 8 in Malta, New York Advances compute capabilities necessary for autonomy advancement Enables leverage of open source software ecosystems​​Enables more/better science return Scalable from small to large systems Enables system resilience: in flight autonomy, adaptive behaviors: AI/ML Efficient and flexible architecture based on a modular open and vibrant industry standards​

This is early/mid-stage (TRL 5) — the most realistic path in is NASA SBIR/STTR, which funds small businesses and research institutions to develop technology aligned with NASA's needs (equity-free, phased funding). Check whether a current SBIR/STTR solicitation topic overlaps with this project's technology area, or contact the project directly (above) to ask.

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