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Completed TRL 5 (started at 3, targeting 5)
Conduct a heavy ion test campaign to characterize single event induced errors and adapt and evolve initial successful FY15 TID methodologies and algorithms. Multiple bit upset rates and possible single event upsets and functional interrupts need to characterized and factored into the overall error correction and mitigation scheme. Evaluate our methodologies/approach on 3D NAND based MLC devices. This is a fundamentally new way to produce NAND devices and is the basis for all future NAND development. Significantly reduces inter-cell parasitic effects improve cell reliability and stability. Error codes are expected to evolve/requires new test HW development. Optimize scrubbing rate, SLC/MLC/Rank Modulation application and in-situ programming and coding channel structure. Determine relative contributions to maximize survivability and define SSD architecture. Fabricate 100mil enclosure and repeat in-situ TID test. Determine maximum possible operational dose for practical operation w/ stand alone FPGA control.
Every NASA mission fundamentally depends on nonvolatile memory, from C&DH to GNC to Science data and from cubesats to Class A projects. JPL has a history of well screened, aerospace grade flash memory causing significant to nearly catastrophic errors on a wide range of missions (MER, MSL). This effort would provide NASA missions with essentially unlimited radiation tolerant non-volatile storage that would completely change the type and quantity of science data collected and enable modern high speed, low power C&DH architectures, particularly required for JPL's strategic roadmap of Mobility and Autonomy. Other potential resources are R&TD, SBIR, DoD, Project funding.
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