Radiation-Tolerant, Scalable Neuromorphic Energy-Efficient Accelerator for Heterogeneous Processor Systems

The accelerator developed by Niobium Microsystems, Inc. (Niobium) is scalable in terms of parallelism and memory capacity, so that it can be targeted towards a variety of platforms, from small battery operated devices to large high-performance compute systems. It also has the ability to perform online learning when operating on neuromorphic workloads, drawing inspiration from the Hebbian learning paradigm. Additionally, the accelerator is designed as a memory-mapped peripheral of a larger heterogeneous System-on-Chip (SoC) and as such it can utilize external memory and implement arbitrarily sized Neural Networks (NNs) and even multiple NNs at the same time. Niobium is also prototyping several different approaches for incorporating radiation-tolerant features in the core by leveraging Niobiums novel digital circuit design flow, and incorporating magnetoresistive random-access memory (MRAM) where appropriate to harden the memory. As part of the Phase II effort, Niobium proposes to proceed with the implementation of the accelerator core with two additional innovations that are crucial to the NASA mission, but also have broader market potential in commercial and defense applications. Specifically, we plan to utilize Niobiums asynchronous circuit design techniques to (1) enable broad Dynamic Voltage Scaling (DVS) for enhanced protection against long-term radiation effects as well as potential improvements in energy efficiency, and (2) incorporate low-overhead radiation-tolerant circuits that protect against transient radiation effects, commonly referred to as Single-Event Transients (SETs), while minimizing the overhead in terms of power, performance and area. Lastly, as part of the implementation effort, Niobium intends to perform a quantitative tradeoff analysis between MRAM and conventional ECC-protected static random access memory (SRAM) with redundancy for the system-level cache of the accelerator. Niobium’s architecture incorporates unique features not found in currently available academic or commercial offerings. The neuromorphic processor employs a tiered memory architecture that can dynamically be configured to run arbitrarily large neuromorphic workloads by leveraging memory resources available both inside the core & on the SoC it is integrated in. It also achieves leading energy efficiency amongst the digital implementation of such processors in existence. While there are numerous neuromorphic hardware solutions for earthbound applications, there are no such hardware options for space-bound platforms. No existing solutions take mitigation of radiation effects into consideration, which is critical for deployment on space platforms. Niobium will implement its accelerator with radiation tolerance as a foundational element of the design. We are designing the chip to run complex workloads AND capable of mitigating soft errors from radiation effects in space environments, especially beyond low Earth orbit, where such phenomena are more pronounced. At the conclusion of this Phase II effort Niobium will deliver a complete test-chip tapeout package. The Niobium test-chip will build on the architecture for a novel neuromorphic accelerator for heterogeneous SoCs which was developed during the Phase I effort. Phase II will focus on Niobium advancing the architecture and furthering the Company’s radiation tolerance flow. This will be achieved through the following tasks (described in the Technical Proposal): P2.0 - Program Management & Meetings P2.1 - RTL Implementation of Neuromorphic Accelerator P2.2 - Simulation and Verification of the RTL P2.3 - Radiation-tolerant library completion P2.4 - Radiation-tolerant flow completion P2.5 - Radiation-tolerant circuit optimization P2.6 - Test-chip definition P2.7 - Physical implementation for test-chip fabrication Milestones will include meetings, interim reports and technical interchange meetings (TIM) focusing on: M1 - Kickoff Meeting; M2 - TIM (+4 months): Detail the initial RTL release (P2.1) and progress towards the development of the rad-tolerant library (P2.3) and flow (P2.4); M3 - TIM (+6 months): Detail final RTL (P2.1), rad-tolerant flow (P2.4), and library development (P2.3); M4 - TIM (+9 months): Detail rad-tolerant optimization (P2.5) and definition of the test-chip (P2.6) including a floor plan; and M5 - Final Report including test-chip tapeout package.

NASA’s missions will establish a permanent presence on the moon this decade (Artemis), followed by similar efforts on Mars. The remote deployment, with long communication latency and limited bandwidth, requires more autonomous systems that can sense their environment, react accordingly and adapt over time. The Niobium chip will enable such capabilities AND allow for withstanding the radiation effects present in space. These demonstrable capabilities are directly transferable to space systems, autonomous vehicles, and other sensor platforms. Niobium is engaging with DoD customers regarding this effort: AFRL/RV, AFRL/RYA, AFRL/RI. Additionally the growing commercial space market is seeking to establish a permanent presence in space which will require rad-tolerant features, not COTS hardware used by LEO solutions.

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