Space Qualified, 3D-Printed, Electronic Assembly Demonstration (SPEAD) Printed Circuit Boards

Recent advances in techniques for Additively Manufactured Electronics (AME) have the potential to produce electronics assemblies that are uniquely compact and conformable, but these techniques have not been proven effective for space applications. Designing and fabricating printed circuit boards (PCBs) that can meet rigorous space flight qualifications specifications is challenging. There are currently no additive manufacturing technologies that can produce PCBs that meet the temperature cycles, shock, vibration, radiation, vacuum, and electromagnetic interference and compatibility requirements. Nanohmics, Inc., in collaboration with Professor Maggie Chen at Texas State University, proposes to leverage advances in 3D printing and photonic curing, materials engineering of highly conductive inks, and integration techniques to demonstrate Space-Qualified, 3D-Printed, Electronic Assembly Demonstration (SPEAD) PCBs. Specifically, the team will demonstrate highly conductive traces fabricated using advanced graphitic inks and novel aerosol inkjet printing, laser-sintered process. In the Phase I effort, the team will demonstrate a SPEAD PCB prototype by designing and fabricating a series of test circuits using graphitic ink on Kapton substrates. The graphitic ink component is based on a high conductivity (6.25x105 S/m) and temperature (>300°C) material. These test circuits will be based on the design of previously space qualified hardware. The prototypes PCBs will demonstrate the integration of commercial-off-the-shelf (COTS) integrated circuits (ICs) in standard surface mount packages with high conductivity traces on a flexible, high temperature substrate. In the Phase II effort, the team will focus on expanding the capabilities of the SPEAD PCB manufacturing process to provide new capabilities, such as multiple layers, integration of passive components, and demonstration of 3D integration to reduce overall component assembly volume.

SPEADs will develop flexible, conformable printed circuit boards that will enable compact and integrated electronic assembly. Any NASA mission that has volume constrained payloads will benefit from this ability to more effectively and utilize the available space.

SPEAD will enable new form factors for electronic assemblies in extreme environments. Potential users include the Department of Defense, specifically the Air Force and Space Force, and energy exploration companies.

This is early/mid-stage (TRL 4) — the most realistic path in is NASA SBIR/STTR, which funds small businesses and research institutions to develop technology aligned with NASA's needs (equity-free, phased funding). Check whether a current SBIR/STTR solicitation topic overlaps with this project's technology area, or contact the project directly (above) to ask.

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