INE Proposal in Response to NASA EPSCOR Rapid Research Response Appendix A: High-Temperature 3-D SiC Integrated Circuit Chip Packaging for Venus Surface Exploration

The objective of this project is to investigate the three-dimensional (3-D) packaging of silicon carbide (SiC) integrated circuits (ICs) for high temperatures of about 465°C and high pressure of about 9.6MPa for Venus surface explorations, specifically to explore the SiC die attach, wirebonding, flip chip, microbump and through-substrate-via (TSV) formation materials and process technologies for 2.5-D chip packaging and 3-D SiC die stacks and integration to withstand the extreme environment on Venus’ surface. We propose to use 3-D IC stacks and integration to package significantly more SiC dies and GaN sensors in one package to save the already precious ceramic printed circuit board (PCB) space and improve electrical and mechanical performance of the chips and package. The developed 3-D SiC IC package will be subjected to a simulated Venus surface atmospheric environment to verify the thermal and structural integrity. A thermal cycling test up to 500°C will be performed for electrical and mechanical failure analysis of the 3-D package including die shear test and wire pull test.

Current Venus landers can only operate on the planet’s surface for a few hours because the commercial electronics fail to work in the extreme Venus surface environment. NASA Glenn Research Center has recently demonstrated that a SiC integrated circuit with more than 100 transistors withstood the simulated Venus surface atmosphere environment for 521 hours. To successfully implement the data collection and telemetry tasks, the SiC integrated circuits need to be carefully packaged to be integrated to the Venus lander. Some preliminary research has been done for basic 2-D packaging of SiC chips including basic die attach and wirebonding. In comparison to millions to billions of transistors in a silicon integrated circuit, a SiC integrated circuit with only several hundreds of transistors need to be densely packed in order to save the precious PCB footprint and improve the electrical and mechanical performance. On the other hand, current advanced 3-D electronic packages are developed for working temperature less than 300°C. The widely used polymer materials in these 3-D package technologies will be burned to ashes on Venus’ surface. To make the 3-D packed chips and sensors work for an extended time (months), different, even new, materials together with new processes must be developed to build the 3-D packages to meet the needs of Venus surface exploration requirements.

The proposed research will make a significant contribution toward the high-performance 3-D packaging of SiC chips and sensors for high temperature, high pressure Venus surface exploration missions.

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