A Radiation Hard Network on Chip Neural Processor with RRAM

Green Mountain Semiconductor Inc. (GMS) is proposing an in-memory solution utilizing non-volatile memory (NVM) in FD-SOI technology for the solicitation H6.22-1123. While rethinking the fundamental architecture of neural networks based on the radiation hard criteria, GMS has developed a robust CIM architecture, incorporating non-volatile RAM with radiation hard characteristics for low-power and low-latency AI edge devices. Existing state of the art solutions utilize separate chips for weight storage and require large amounts of on-chip SRAM in order to load weight information and process data. While off-chip weight storage does allow for various types of memory to be used based on user application, the penalty comes in the form of weight transfer on-chip, which is not generally accounted for in the power numbers and efficiency touted by neural network chip designers. In order to limit weight movement power cost, neural networks store large amounts of data in SRAM in order to perform large batch operations. This, in itself, introduces another costly weak point with regards to space applications, that being the storage of information for extended periods of time in SRAM memory cells. GMS has been able to develop a CIM architecture that eliminates the von Neumann bottleneck by integrating all memory for weight storage on chip, significantly reducing weight movement and decreasing the total amount of SRAM, as well as the length of time that data is stored in SRAM. This unique design allows for accelerated AI inferencing, particularly for Convolutional Neural Networks (CNN), outperforming other state of the art architectures. Focusing on SRAM reduction coupled with circuit design techniques, using radiation hard NVM and radiation hardened logic the chip reaches radiation target levels required for deep space computing. The proposed innovation is a radiation hardened network-on-chip hardware accelerator optimized for state of the art convolutional neural networks for tasks such as image classification. RRAM memory is used for on-chip weight storage, paired with an innovative architecture and rad-hard by design techniques. Anticipated performance metrics include 33.1 Tops/W in a 22FDX technology improving to 63.1Tops/W in 12FDX. The chip targets ultra fast (< 100us) power on time, allowing for deep sleep to inference mode without penalty and low standby power (less than 1mA). Latency is < 10ms, and batching is not needed for high efficiency. This gives the part the ability to process images at the edge on demand. Current state of the art accelerators have several watts of standby power, require batching for performance, and are not radiation hard. The target for the chip is 200 kRAD tolerance and a maximum 1x10^-3 number of faults per minute. Applications for such performance range from satellites to lunar missions to deep space, avionics and even human based space missions for edge AI computing. The technical objectives of this Phase II are to design and fabricate macros for commonly used subcomponents of the neuromorphic architecture. Tests will be performed on this early test chip focusing on specifications for functionality and radiation tolerance. The macros will include digital functional blocks, such as Multiplier, Accumulator, and Activation functions, that operate as the repeatable blocks that represent a node within a neural network. Other core structures to the architecture, such as RRAM bit cells with sense/write circuits for the RRAM, will be fabricated with the goal of testing for specifications. This early test chip tapeout will allow for expedited learning on identified high risk elements of a full featured prototype, thereby reducing overall time of development and increasing the confidence of a first time right design. Alongside this design work, progress will be made on the top level architecture of the fully functional neuromorphic prototype chip. All of these technical objectives and deliverables will further this project to ultimately create a neuromorphic inference chip that performs at the state of the art in a radiation heavy environment. 

Potential NASA applications include any critical image processing mission where device functionality is imperative. This includes deep space missions subject to solar flares. Flight navigation is of particular interest in this respect. Habitable Worlds Observatory would be a prime candidate, requiring long life, low power, and edge computing capabilities. Lunar missions can also benefit from the innovation's low power, low leakage, and power-down, instant-on capabilities, especially when operating in extended critically low power conditions. Non-Nasa applications may include a multitude of terrestrial and near space applications: Robots working in environments with elevated radiation levels (nuclear power plants, cleanup operations following nuclear accidents or acts of warfare) • Life-critical systems such as operating room equipment and implanted medical devices • Sensitive and safety-critical automotive controls • Aerospace electronics

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