Radiation Hardened Structured ASIC Platform for Rapid Chip Development for Very High Speed System on a Chip (SoC) and Complex Digital Logic Systems

Radiation Hardened Application Specific Integrated Circuits (ASICs) provide for the highest performance, lowest power and size for Space Missions. In order to dramatically reduce the development cycle and reduce the cost to tapeout Rad Hard ASICs, we propose a Structured ASIC approach. In this approach we fix an array of complex logic cells and provide a fixed Area Array for I/O pads supporting in excess of 400 CMOS GPIO pins. In addition, we fix the power grid and the pins associated with power (core and I/O) and ground. Thus, we require only routing in a subset of the metal layers in order to configure the Structured ASIC to a specific design. This leads to substantial reduction in design and verification time to tapeout, and results in reduced cost by requiring a subset of Mask changes per design. In this work, we will build on existing 90nm Silicon proven Radiation Hardened Structured ASIC platform and develop a Structured ASIC platform at the 45nm SOI technology node with the objective to increase the clock speeds to hundreds of MHz with SEU mitigation in sequential logic. We will also use High Density Interconnect (HDI) for packaging the Die in BGA and LGA packages. The HDI design does not change for each configuration of the Structured ASIC so that the same benefits of Structured ASIC are extended to packaging the part with high pinout and high speed I/O requirements eliminating layout design costs.

With the rapid development cycle to manufacture packaged Radiation Hardened ASIC chips with the increased speed performance and dramatically lower power, NASA can enable interplanetary and long term low Earth orbit missions that support 32 bit and 64 bit Systems on a Chip (Soc) with high speed networking and multiple sensor bus support. These SoC ASICs will enable more complex sensor integration with the C&DH. Designs can be adapted to various bus protocols proposed and in use for CubeSat missions. The reconfigurable high gate count, multi-MHz SEU immune sequential logic, embedded RAM and mask programmable ROM capability, allows for high performance processors to be designed to meet mission requirements in rapid production cycles with proven in Silicon fabric and standard Die I/O and robust high pin count packaging. The 6 month to Silicon cycle, will allow NASA to meet mission schedule without sacrificing speed and power requirements and also enable missions that were otherwise impossible to achieve in harsh radiation environments.

Commercial companies that deploy Geosynchronous satellites will benefit from the capability to design Rad Hard ASICs that can be configured in a rapid production cycle to meet specific demands for interfacing to communication systems over high band width busses. The dramatic cost reduction with Structured ASIC will make possible missions that required ASICs but were cost prohibitive. The Rad Hard Structured ASIC approach will also allow commercial CubeSat missions to extend beyond low Earth orbit to interplanetary missions that requite greater TID and SEU immunity. Also commercial missions with high cost payloads can plan longer term low earth orbit missions using Rad Hard, high performance low cost ASICs in place of COTS parts that will fail.

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