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OrFPGA: An Empirical Performance Tuning Tool for FPGA Designs

Completed TRL 6 (started at 3, targeting 6)

Description

In this Phase II STTR project, RNET and its subcontractors are proposing to fully develop an empirical performance optimization tool called OrFPGA that efficiently explores the "user tunable" parameter space of an FPGA design and assists in deducing the near optimal design in terms of timing score, device utilization, and power consumption. The tunable parameter space will include IPCore parameters, HDL and HLS code constructs, and parameter settings for the vendor's design tools. Special automation tools will be developed to facilitate annotation of HDL/HLS code and design tool scripts. The computational magnitude of empirical performance tuning of FPGA designs will be addressed by novel machine learning based search algorithms requiring minimal empirical evaluations, computational steering, leveraging intermediate performance analysis results, and parallelization techniques. The tool will support specification of prioritized performance metrics, easy-to-use interfaces for defining the parameter space, and intuitive visualization of performance models. The user will be able to automatically deduce the best environment settings the chip and also accurately identify the optimal power consumption through optional real-time power monitoring. The benefits of the tool to NASA will be demonstrated in terms of performance metrics and cost benefits (user productivity) using real NASA designs that are used in space missions.

Benefits

The OrFPGA tool can be used by hardware engineers at NASA and its Prime Contractors to get the incremental performance optimizations required for closing critical FPGA designs in space applications. Potential NASA applications include FPGA implementations on SpaceCube platforms, LCRD algorithms, Pinpoint landing vision components and stereo disparity implementation. The tool will improve both FPGA design performance and developer productivity. The tool will be available as a standalone alone as well as an add-on feature in the existing FPGA design tools.

Other potential markets could include DoD and its Prime Contractors, DOE, and DHS on the government side as well as medical, communication, and banking industries on the industry side. Example applications include military satellites, portable medical devices, and high frequency trading systems.

Details

Technology areaFlight Computing and Avionics > Avionics Component Technologies > High-Performance Field-Programmable Gate Arrays
ProgramSmall Business Innovation Research/Small Business Tech Transfer (SBIR/STTR)
Lead organizationRNET Technologies, Inc., Dayton, OH
Start date2014-09-17
End date2017-09-16

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How to get involved

This is early/mid-stage (TRL 6) — the most realistic path in is NASA SBIR/STTR, which funds small businesses and research institutions to develop technology aligned with NASA's needs (equity-free, phased funding). Check whether a current SBIR/STTR solicitation topic overlaps with this project's technology area, or contact the project directly (above) to ask.

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