Fault Tolerant RISC-V Flight Computer with Coprocessor Support (RadPC+Coprocessor)

The RadPC computer technology provides reliability and performance for small spacecraft that have power and cost constraints. The base version of RadPC implements a RISC-V processing architecture on a commercial-off-the-shelf (COTS) field programmable gate array (FPGA). Using a COTS FPGA provides an inherent level of total ionizing dose (TID) immunity due to the small feature sizes of modern transistors. Single event effects (SEEs), which are the dominant fault mechanism in modern devices, are handled using a set of patented fault-recovery procedures that include redundancy and output voting, redundant CPU register arbitration, memory scrubbing, configuration memory error correction codes, and partial hardware reconfiguration of the FPGA. Implementing the RadPC computer on a COTS FPGA provides increased reliability at a cost-point that is feasible for small spacecraft. 

In order to take advantage of the signal processing capability of an FPGA, the unused hardware resources on the device are bundled into a “coprocessor” block that is coupled with RadPC on the same device. The co-processor can perform rapid signal processing algorithms by taking advantage of massive parallelism and optimized hardware circuitry. When coupled with RadPC, the signal processing coprocessor can be controlled using standard software and RadPC can monitor the coprocessor for faults and initiate recovery procedures in the event of an error. The combined approach of the fault-tolerant RadPC computer on the same FPGA as a fully integrated coprocessor can provide increased on-orbit computation while simultaneously achieving reliability beyond the state of the art in small spacecraft computers.

Problem Statement 
Small spacecraft are, by design, resource and cost constrained. Current small spacecraft computers typically don’t contain fault tolerance because these missions can’t afford the expensive “radiation hardened” processors used in larger missions and don’t have the power availability to implement common fault recovery procedures such as redundancy. This leaves small spacecraft in the situation that they are not tasked with critical applications such as autonomy or with algorithms such as artificial intelligence or machine learning. The RadPC+Coprocessor technology aims to deliver the needed reliability for small spacecraft to take on critical mission tasks while simultaneously achieving a price that is cost feasible for these types of missions. 

Technology Maturation 
The base RadPC computer has been matured through more than a decade of university funding at Montana State University, where it achieved TRL-8 through a lunar demonstration in 2025. The RadPC+Coprocessor technology has been matured to TRL-6 through SBIR funding at Resilient Computing. The hosted orbital flight provided by NASA Flight Opportunities will mature the RadPC+Coprocessor technology to TRL 8 through an in-space demonstration of the technology in its final commercial form processing real image data.

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