High-Speed, Low Power 256 Channel Gamma Radiation Array Detector ASIC, Phase I

Building on prior success in detector electronics, we propose to design and fabricate a 256 channel readout ASIC for solid state gamma radiation array detectors having a power consumption of less 100 microW/pixel, an event detection throughput of more than 10,000 events/sec, and a dynamic range of 20-600KeV, while providing a spectral resolution of 1% or less in a footprint of less than 12 x 12 mm. This will allow the creation of high-speed 20 x 20 mm CZT detectors with 256 to 512 pixels (1 mm or less pitch). Starting with prior proven designs, we will introduce an innovative, patent-pending readout scheme that reduces digitization to only one signal per channel. We will also replace polling methods with sparse access and an innovative technique that can keep most of the pixels operating while reading out data. These innovations may increase the ASIC event detection rate by orders of magnitude while reducing system power and processing requirements. These innovations are essential for upgrading current gamma detection technology for future missions. There exists no ASICs today that can come close to achieving this performance.

This is a mature technology (TRL 7+) — the realistic path in is usually NASA's Technology Transfer Program: licensing an existing NASA patent, or a Space Act Agreement to use NASA facilities/expertise directly. NASA also runs a startup licensing program with no upfront fee for companies formed to commercialize a specific NASA technology.

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