Modular, Fault-Tolerant Electronics Supporting Space Exploration, Phase II

Modern electronic systems tolerate only as many point failures as there are redundant system copies, using mere macro-scale redundancy. Fault Tolerant Electronics Supporting Space Exploration (FTESSE) creates an electronic design paradigm using reprogrammable FPGAs to create swappable Circuit Object Blocks (COBs) -- analogous to software objects -- for the first time enabling redundancy on a micro-scale. The result is an increased tolerance of point failures by several orders of magnitude over traditional approaches. In the FTESSE approach, FPGAs are partitioned into COBs (groups of gates), each performing a specific function. Bad areas can be mapped like the bad sector data on a disk drive, enabling COBs to be placed in areas of working gates to recover system performance. Hardware tested during Phase I verified point failures could be introduced into an example circuit and corrected. As in the Phase I model, circuits to be monitored reside on a Slave FPGA, and a Master FPGA monitors outputs of all COBs, sensing faults and mapping non-working gates on the Slave FPGA. The Master is a rad-hard, triple mode redundancy (TMR) FPGA, but the Slaves need not be, opening the doors to higher performance applications while maintaining high levels of fault tolerance.

This is a mature technology (TRL 7+) — the realistic path in is usually NASA's Technology Transfer Program: licensing an existing NASA patent, or a Space Act Agreement to use NASA facilities/expertise directly. NASA also runs a startup licensing program with no upfront fee for companies formed to commercialize a specific NASA technology.

None of these are guaranteed paths for this specific project — TechPort itself doesn't have an "apply" button. Reaching out to the contact(s) above with a specific question is usually the fastest way to find out what's actually open.