Software Defined Common Processing System (SDCPS), Phase II

Coherent Logix, Incorporated (CLX) proposes the development of a Software Defined Common Processing System (SDCPS) that leverages the inherent advantages of an integrated parallel processing architecture. Targeting a specific waveform (TBD) specified by NASA-GRC in terms of a high level functional model, e.g. Simulink, the study aims to examine system performance in a reference implementation based on the HADS2 development system configured for this purpose to include the HyperX signal processor, data converters and General Purpose Processor (GPP). Waveform implementation will be executed in stages: (i) port an implementation to the signal processing complex consisting of a single path per functional block (consuming multiple resources depending on the complexity of each block) (ii) extend the design to account for N-modular path redundancy aimed at enhancing system reliability (iii) integrate in the reference platform to enable real-time performance assessment, e.g. resource utilization, throughput efficiency and emulated radiation tolerance. This effort is supported by extensive development underway at CLX to deliver a line of extremely high-performance per watt, runtime configurable signal processors. Based on a multi-core architecture, the intended processing system will enable model based waveform development applicable across a range of fault tolerant mission classes without sacrificing real-time throughput performance.

This is a mature technology (TRL 7+) — the realistic path in is usually NASA's Technology Transfer Program: licensing an existing NASA patent, or a Space Act Agreement to use NASA facilities/expertise directly. NASA also runs a startup licensing program with no upfront fee for companies formed to commercialize a specific NASA technology.

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