High Performance Ultra Low-Power ADCs and DACs

The objective of the Phase-I research is to design a multi-GHz high bandwidth Delta Sigma Analog-to-Digital and Digital-to-Analog converter using a deep sub-micron CMOS process. Since the Delta Sigma Modulation ADC samples in the multi-GHz range, direct sampling and conversion to digital of post LNA Microwave signals is possible. By targeting the ADC on a CMOS technology node (90nm, 65nm or 45nm), a complete all digital radio receiver and demodulator can be implemented on the same System on a Chip that performs host interface and higher network level protocols. Using Delta Sigma Modulation at GHz sampling rates eliminates the anti-aliasing filter requirement. The all digital receiver eliminates I/Q imbalance due to the receiver and DC offset introduced by zero-IF architectures. In order to support multi GHz sampling rates in CMOS, advanced time interleaving, parallel Delta Sigma Modulators and shared integrator architectures are considered. Using Micro-RDC RHBD cells and design experience the digital filtering and decimation of the high frequency bit stream are hardened. The baseband filtering is implemented with temporal latch technology for SEU immunity. In this research various hardening techniques will be used to harden the analog sub-components in the Delta Sigma Modulator including investigating pipelining and parallel processing architectures for filtering and decimation which also address low power requirements.

In the commercial sector and non-commercial Military sector, an ADC that directly samples and converts Microwave signals (post LNA) to digital for all-digital processing is in high demand. Many IC vendors strive to minimize the analog RF front end and reduce as much complexity in the analog domain to increased complexity in the digital domain. Since our design is based on deep sub micron technology nodes, potential customers who license Micro-RDC's Delta Sigma Modulation IP can design all inclusive RF digital Radios within Systems on a Chip achieving near complete elimination of the analog RF components. This will have a huge impact on the cellular market, WiFi and WiMax market. In particular, since we are targeting the S-Band Microwave systems, the ADC can be used for direct conversion of the popular 2.4 GHz WiFi bands and many cellular bands to digital. This design will enable single chip solutions to those markets. The fact that designs are all digital and in many cases eliminate complex calibration requirements in manufacturing, in addition to eliminating low yield issues in analog IC's, will drive down the cost of communication devices and equipment.

The GHz sampling rate, high bandwidth, and high resolution radiation hardened Delta Sigma modulation ADC's implemented on a CMOS technology node (90nm, 65nm, or 45nm) paves the way for the elimination of RF analog front end circuits in S-band Microwave digital communication transceivers. In addition the ADC and DAC can be used in direct conversion of signals in Advanced Synthetic Aperture Radar, Advanced Interferometer for Surface monitoring, ice topography, and hydrology. Digital beam forming (DBF) systems require an array of ADCs. According to NASA the requirements are 1.5 GHz band width and an ENOB of 12 bits. The power requirement is 100 mW. The Delta Sigma Modulation ADC proposed in Phase I and completed in Phase II exceeds these requirements. Since the proposed Micro-RDC ADC will be designed with Micro-RDC's RHBD cell library (90nm or 65nm) we hope to meet the requirements for harsh radiation environments (the Europa Jupiter System Mission anticipates > 3 MRad(Si) total ionizing dose (TID) ).

This is early/mid-stage (TRL 5) — the most realistic path in is NASA SBIR/STTR, which funds small businesses and research institutions to develop technology aligned with NASA's needs (equity-free, phased funding). Check whether a current SBIR/STTR solicitation topic overlaps with this project's technology area, or contact the project directly (above) to ask.

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