A Novel Approach to Improving the Radiation Hardness of SiC Power Devices

Silicon Carbide Technology for power semiconductors offers a significant improvement in capability that will allow systems to operate at higher voltages and temperature and offer greater efficiency. However, the current state of the art for this technology proves to have significant issues that prevent its use in the space environment. Specifically the susceptibility to heavy ion damage that requires significant derating of the devices to a point that makes their use not practical. The problem for SiC MOSFET?s appears to make these devices unusable in space system due to the extremely low operating voltage where damage occurs within the device. This proposal will focus on SiC MOSFET and propose a novel approach to significantly improve the heavy ion performance to a level where the use of SiC MOSFET?s constructed using this approach would be feasible in most space applications. Semicoa is teamed with General Electric Global Research Center (GEGR) to solve this issue and provide a pathway to bring these devices to the space market fully qualified to military specifications. The focus of this effort will be to further optimize the hardening techniques being investigated by GEGR and develop a novel approach to depositing the gate oxide with Atomic Layer Deposition (ALD) techniques. This approach will allow the use of a much thicker gate oxide, while maintaining the total dose hardness characteristics, and provide significant improvement to the heavy ion performance. The challenge will be addressing the interface between the dielectric and the semiconductor. It is believed that the ALD process using a High-K dielectric material will lower the interface state density to achieve the total dose hardness while at the same time provide for a significant improvement in the heavy ion performance.

The development and integration of high voltage/high temperature components that can be space qualified will lead to increases in system level performance as they will tend to increase efficiency and decrease mass at the system architecture level. Such performance improvements are necessary if NASA is to realize several operational concepts such as very high power Solar Electric Propulsion (SEP). In a simplistic but specific realization, higher voltage parts allow power generation at higher voltages on the arrays themselves, this higher voltage allows for the same power to be transferred at lower current thereby reducing cable mass at the system level.

Silicon MOSFET?s seem to be reaching the ?end of the road? as far as improvements to the technology for power, speed and performance. SiC MOSFET technology offers high-temperature and high-power operation far superior that that of Silicon MOSFETs. It is generally felt that SiC is early in its life cycle and there are many applications that could benefit from this technology. SiC extreme high electron mobility and low temperature coefficient enables a very low RDS(ON). This device would have superior switching characteristics due to the high critical field, high electron mobility, high saturation velocity and low gate-drain capacitance of the SiC device. This also allows for short delay times and excellent controllability in low duty-cycle applications. SiC devices also have significantly lower output capacitance when compared to Silicon MOSFET?s of similar RDS(ON). SiC offers the benefits of the least power consumption while providing for the lowest energy loss at extremely high temperatures requiring limited external cooling.

This is early/mid-stage (TRL 3) — the most realistic path in is NASA SBIR/STTR, which funds small businesses and research institutions to develop technology aligned with NASA's needs (equity-free, phased funding). Check whether a current SBIR/STTR solicitation topic overlaps with this project's technology area, or contact the project directly (above) to ask.

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