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Completed TRL 6 (started at 5, targeting 6)
The goal of this project is to mature the technology readiness of a radiation tolerant smallsat computer system for a subsequent orbital flight demonstration. The system is implemented with commercial off-the-shelf (COTS) field-programmable gate arrays (FPGAs) to provide space-computing performance that improves upon existing radiation hardened processors. Commercial FPGAs are now yielding acceptable levels of total ionizing dose immunity due to the thinning of gate oxides and relative deepening of isolation trenches. If a single event effect mitigation strategy can be implemented on COTS FPGAs, then reliable, high performance space computing can be accomplished at a fraction of the cost of existing radiation hardened processors.
This technology will increase on-board processing at a significantly reduced cost over existing systems.
Listed on TechPort itself — the most direct way to ask about this specific project.
This is early/mid-stage (TRL 6) — the most realistic path in is NASA SBIR/STTR, which funds small businesses and research institutions to develop technology aligned with NASA's needs (equity-free, phased funding). Check whether a current SBIR/STTR solicitation topic overlaps with this project's technology area, or contact the project directly (above) to ask.
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