Reducing the Cost of Flight Data Systems with the RISC-V Computer Architecture (RISC Reduction)

The “Reducing the Cost of Flight Data Systems with the RISC-V Computer Architecture” IRAD will begin the process of porting the CFS to the free and open-source RISC-V Instruction Set Architecture (ISA) processor.

With the increasing use of IP core FPGA based processor systems, the RISC-V architecture has the potential benefit of lowering data system costs by eliminating associated licensing fees required by other processor architectures. The RISC-V architecture would be a great companion to the open source and collaboration efforts of the cFE/CFS software. Beginning the CFS porting effort to provide support for the RISC-V architecture will reduce development time and save cost and schedule for future missions utilizing the RISC-V processor architecture. The use of the RISC-V architecture and its open sourced tools will eliminate costly IP that locks you in to a single vendor provide solutions.

This is early/mid-stage (TRL 3) — the most realistic path in is NASA SBIR/STTR, which funds small businesses and research institutions to develop technology aligned with NASA's needs (equity-free, phased funding). Check whether a current SBIR/STTR solicitation topic overlaps with this project's technology area, or contact the project directly (above) to ask.

None of these are guaranteed paths for this specific project — TechPort itself doesn't have an "apply" button. Reaching out to the contact(s) above with a specific question is usually the fastest way to find out what's actually open.