Rad-Hard and ULP FPGA with "Full" Functionality

Our vision for this NASA proposal is to develop a rad-hard and ultra low power (ULP) reconfigurable FPGA that will have

The rad-hard and ULP FPGA can be used by other agencies, such as, MDA and DoD for satellite applications and high-altitude airborne applications. Because the FPGA will consume very low power, it can also be effectively used in no-radiation environments (commercial applications such as cell phones, remote sensor platforms, hand-held devices, etc.) where the major requirement is extremely low power consumption and extended battery life.

One of the limiting factors for the EJSM is the mitigation of TID radiation. Both the JEO and JGO will be subjected to various doses of radiation during the mission. In fact, the radiation design point for the JEO is 2.9 Mrads (Si) over its nine year mission. Hence, electronic components and processors (FPGAs, ASICs, etc.) that are capable of operating in such environment will be desirable. The rad-hard ULP FPGA that will be developed is capable of operating in such environments and also consume low power.

This is early/mid-stage (TRL 4) — the most realistic path in is NASA SBIR/STTR, which funds small businesses and research institutions to develop technology aligned with NASA's needs (equity-free, phased funding). Check whether a current SBIR/STTR solicitation topic overlaps with this project's technology area, or contact the project directly (above) to ask.

None of these are guaranteed paths for this specific project — TechPort itself doesn't have an "apply" button. Reaching out to the contact(s) above with a specific question is usually the fastest way to find out what's actually open.