Scalable Parallel Algorithms for Formal Verification of Software

We will develop a prototype of a GPU-based parallel Binary Decision Diagram (BDD) software package. BDDs are a data structure that satisfies some simple restrictions, resulting in a unique representation of a Boolean function regardless of its actual implementation. This property of BDDs allows the efficient solution of many problems. The proposed tool will exploit multi-core CPUs and the thousands of stream cores in the latest graphics processors (GPUs) , which were made accessible to programmers through specialized software development kits. These large numbers of stream cores in GPUs, and the possibility to execute non-graphics computations on them, open unprecedented levels of parallelism at a very low cost. In the last 8 years, GPUs had an increasing performance advantage of an order of magnitude relative to x86 CPUs. Furthermore, this performance advantage will continue to increase in the next 20 years because of the scalability of the chip manufacturing processes. The technical objectives will be to efficiently exploit the GPU parallelism in order to accelerate the execution of a BDD package, and to explore hybrid approaches that will combine this GPU-based BDD package with our GPU-based parallel SAT solver that we are currently developing in a NASA SBIR Phase II project. The goal will be to achieve increased speed, as well as scalability for much larger state spaces when formally verifying complex software for space applications. We anticipate increase in both speed and scalability by 1 – 2 orders of magnitude by the end of Phase I, and 3 – 4 orders of magnitude by the end of Phase II, compared to the current approaches.

The proposed project will result in increase of both speed and capacity when formally verifying complex software. The techniques will also be applicable when formally verifying hardware, proving the correctness of radiation-hardening transformations for digital circuits, mapping of software for execution on reconfigurable architectures such as FPGAs, logic synthesis, power and timing analysis of circuits, scheduling, planning, and solving of constraint optimization problems.

The non-NASA customers will have the same benefits from the technology as NASA. The commercialization will target the major semiconductor, software, and Electronic Design Automation (EDA) companies, as well as NASA prime contractors, aerospace and weapons manufacturers, and all companies that develop embedded systems.

This is early/mid-stage (TRL 4) — the most realistic path in is NASA SBIR/STTR, which funds small businesses and research institutions to develop technology aligned with NASA's needs (equity-free, phased funding). Check whether a current SBIR/STTR solicitation topic overlaps with this project's technology area, or contact the project directly (above) to ask.

None of these are guaranteed paths for this specific project — TechPort itself doesn't have an "apply" button. Reaching out to the contact(s) above with a specific question is usually the fastest way to find out what's actually open.